In synchronous data processing systems clocked latching circuits are used to receive and hold data values for a portion of a clock cycle such that the data values can be passed through the system in a synchronous and deterministic way. Latching circuits are conventionally formed of feedback loops with clocked pass gates for connecting a data input to the feedback loop or isolating the data input from the feedback loop. In this way the feedback loop is updated in response to the clock signal.
A feedback loop should be able to reliably hold the data value and yet be able to be overwritten by a new data value. Conventional latches had transmission gates at their inputs and feedback loops that were clocked by the clock signal. This allowed the feedback loop to be broken as the clock signal changed phase facilitating overwriting of the data value in time with the clock signal. A drawback of this approach is that where the data value does not change, some switching of devices occurs within the feedback loop in response to the clock signal changing, this is expensive on power. Furthermore, the transmission gates and the clocking of the feedback loop require both a clock signal and an inverted clock signal for their control, the generation of an inverted clock signal requires buffers on the clock tree which again is expensive on power.
In this regard within many processing systems flip flops formed of two latching elements typically consume much of the power and account for much of the logic area. Thus, a reduction in their power consumption is desirable, however, any increase in area of a flip flop will have a significant effect on the area of the circuit.
One solution that has been considered is to replace the transmission gates with simple transistor pass gates and use a differential device with data and complementary data inputs such that an inverted clock signal is not required. A problem with such a solution is that overwriting of the feedback loop with a new data value is difficult and the yield of such a system may not be high. Toshiba considered this problem in their paper “A 77% Energy-Saving 22-Transistor Single-Phase-Clocking D-Flip-Flop with Adaptive-Coupling Configuration in 40 nm CMOS” by Chen Kong The et al. published on pages 338-340 of the Digest of Technical Papers of the 2011 IEEE International Solid-State Circuits Conference, and found that for a master slave flip flop, the master latch with PMOS pass gates was not reliably overwritten with new data when designed without the clocked feedback loop. It provided a solution for this with a master latch having PMOS and NMOS transistors arranged in parallel on either side of the feedback loop. These PMOS and NMOS transistors were controlled by the data signal, such that when it changed value the feedback loop was disturbed and the state-retention coupling weakened during the transition. In particular, the paper notes that the provision of the NMOS transistor turning on the side of the loop to be discharged helps the discharge of this side.
A drawback of this solution is the additional transistors required for the master latch, although this was compensated for in some regard by the reduced number of transistors required for the pass gates which had replaced transmission gates with simple transistors.
It would be desirable to have a latching circuit with low power consumption particularly during low data activity that has an acceptable yield.